LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisation.

arXiv:2610.16625v1 Announce Type: new Abstract: Post-route FPGA timing closure remains expert-dependent and computationally expensive. We present LATCH (LLM-Assisted Timing Closure Harness), a two-layer framework that separates large language model (LLM) orche